End-to-End Validation for AI System Interconnects

At DesignCon 2026 in Santa Clara, Keysight will present end-to-end test and measurement solutions spanning chiplets, high-speed interconnects, memory, and emerging AI fabrics, addressing physical limits and system-scale performance challenges in next-generation AI platforms.

From chiplets to system-scale confidence
Designing AI systems increasingly requires validation across multiple abstraction levels, from advanced packaging and chiplets to board-level interfaces and full network fabrics. Keysight’s demonstrations focus on enabling engineers to de-risk designs early by combining design workflows, physical-layer validation, and interoperability testing.

The showcase emphasizes a continuous validation journey, starting with multi-die interconnect design and extending to benchmarking 1.6T-class AI networks, ensuring that individual components perform reliably when integrated at system scale.

Accelerating chiplet and 3D IC development
The Chiplet 3D Interconnect Designer demonstration highlights a workflow for developing multi-die interconnects used in AI accelerators and high-performance processors. By integrating design and validation tools, the approach supports faster exploration of interconnect architectures, helping engineers manage signal integrity and power delivery challenges associated with dense 3D IC packaging.

Pushing signal integrity boundaries
To address the bandwidth demands of next-generation infrastructure, Keysight will demonstrate signal integrity validation at speeds up to 3.2T. The setup combines the Physical Layer Test System (PLTS2026) with the NA5307A frequency extender operating to 250 GHz. This configuration illustrates the measurement accuracy required to characterize channels and components operating near physical limits, supporting earlier validation and reduced time-to-market.

Memory interfaces for AI workloads
Memory performance is a critical constraint for AI systems. Keysight’s memory validation demonstrations include a live DDR5 system for mainstream electrical testing and a GDDR7 PAM3 signal integrity setup. The latter uses a new signal-to-noise-and-distortion ratio (SNDR) and jitter measurement suite to streamline compliance testing and debugging for high-bandwidth memory interfaces.

PCIe^® and emerging modulation strategies
Keysight will showcase next-generation PCIe^® test solutions targeting PCIe 7.0, covering both electrical and protocol-layer validation. Using the UXR-Series oscilloscope, M8050A BERT platform, and PCIe test software, the demonstration focuses on accelerating debug, improving margin analysis, and enhancing link reliability for high-speed PAM4 implementations.

In parallel, the 448 Gbps pathfinding demonstration explores future signaling strategies. By generating and analyzing PAM4, PAM6, and PAM8 signals with the M8199B arbitrary waveform generator and N1046A electrical channel module, researchers can evaluate modulation trade-offs and optimize interconnect architectures for higher data rates.

Validating 1.6T AI interconnects
The validation journey culminates with demonstrations focused on 1.6T-class interconnects for AI networks. The INPT-1600GE benchtop test system is used to validate bit error rate (BER) and forward error correction (FEC), measure link quality, and benchmark AI workloads. These capabilities address the need to verify performance and reliability as AI systems scale across racks and data centers.

Additional demonstrations highlight automation and compliance solutions for emerging AI fabrics, including UALink and scale-up Ethernet. These solutions support automated workflows, expanded measurement coverage, and streamlined calibration for conformance testing and debug of 1.6T electrical networking interfaces.

Event details
DesignCon 2026 takes place from February 24–26, 2026, at the Santa Clara Convention Center. Keysight’s demonstrations will be located at Booth 1039, providing engineers with a system-level view of how advanced validation strategies can reduce risk and accelerate deployment of AI hardware platforms.