Ceva Unveils Next-Generation NeuPro NPU Portfolio

Semiconductor design teams face escalating architectural bottlenecks as artificial intelligence workloads transition from static classification models toward dynamic, multimodal, and agentic foundation architectures. In edge devices, robotic nodes, and autonomous machinery—collectively termed Physical AI—system architects must balance continuous real-time perception against strict thermal envelopes and battery capacities. Concurrently, enterprise data centers face compounding memory-wall and data-movement bottlenecks during large language model inference. Traditional monolithic neural processing unit designs often force silicon vendors to license disparate, non-standardized architectures for varying compute tiers, multiplying software engineering overhead, driver maintenance, and toolchain fragmentation. Overcoming these integration constraints requires a scalable, unified neural processing architecture supported by a singular software stack that spans the computing spectrum from microwatt sensing to megawatt infrastructure.

Scalable Hardware Architecture and Numerical Efficiency
To bridge computing tiers across the smart edge and cloud environments, Ceva introduced its next-generation NeuPro neural processing unit (NPU) portfolio. Built upon an upgraded core microarchitecture, the generation delivers up to two times higher AI throughput per square millimeter and achieves a 50 percent improvement in energy efficiency relative to first-generation NeuPro IP.

The updated architecture incorporates advanced low-bitwidth numerical formats, natively supporting four-bit and eight-bit floating-point data types (FP4 and FP8) alongside INT formats. By leveraging micro-precision datatypes, the architecture reduces external memory bandwidth consumption and minimizes off-chip data movement. Compute efficiency is further enhanced by tensor reshaping mechanisms that maximize multiply-accumulate (MAC) utilization across irregular matrices. To accommodate modern generative network topologies, the architecture incorporates hardware-assisted memory management—featuring dynamic tensor shapes and paged Key-Value (KV) cache handling—alongside native execution support for Mixture-of-Experts (MoE) models, linear attention algorithms, and pre-quantized open-source checkpoints.

Tiered Product Portfolio and Infrastructure Expansion
The next-generation NeuPro portfolio organizes compute capabilities into four scalable cores:

All four tiers operate under a common architectural model and are managed via a single unified software development kit (SDK). This software standardization allows semiconductor vendors to deploy multiple distinct NPU cores across a single heterogeneous system-on-chip or migrate IP across multi-generational roadmaps without rewriting underlying application code.

Additional Context
This section details technical specifications and competitive benchmarking not included in the original product announcement.

In neural processing architectures governed by edge and cloud inference benchmarks (such as MLPerf Mobile and MLPerf Inference), memory traffic often accounts for the majority of total system power dissipation. Implementing paged Key-Value caching within the hardware execution pipeline directly mitigates the memory fragmentation caused by dynamic sequence lengths in multi-turn generative models. Rather than allocating contiguous static memory blocks for worst-case context lengths, paged caching dynamically allocates virtual memory pages for attention tokens, reducing memory overhead and preventing out-of-memory faults during long-context processing. Furthermore, adopting FP4 and FP8 precision formats aligns with industry numerical standards established by the Open Compute Project, offering a trade-off that preserves model accuracy within fractions of a percent while reducing weights storage footprint compared to standard 16-bit floating-point formats.

Within the licensable neural processing intellectual property sector, Ceva’s expanded NeuPro portfolio benchmarks against established edge and infrastructure IP platforms from Arm (Ethos-U and Ethos-N series), Synopsys (DesignWare ARC EV and NPX6 NPU families), and Imagination Technologies (PowerVR Series4). While competitors such as Arm have traditionally maintained architectural divisions between their micro-controller-class microNPUs (Ethos-U55/U65) and enterprise application cores, Ceva unifies the microarchitecture across both the milliwatt domain and data center fabric. By engineering NeuPro Ultra to embed directly into high-bandwidth memory controllers and intelligent networking silicon, Ceva competes alongside emerging near-data-processing architectures, addressing data movement latency directly within the memory hierarchy.

Edited by Romila DSilva, Induportals Editor, with AI assistance.